A multiple line system to which a plurality of data processing units are connected can also be designated as a multicomputer system when the data processing units involved are computers. In order to simplify the following description, a data processing unit which can be switched into a multiple line system is also designated as a processor, although the switching in of other types of data processing units is also conceivable. Moreover, the multiple line system will be designated in the following as a "bus" in accordance with the terminology familiar to one skilled in the art.
An internal memory can belong to a data processing unit or processor connected to a bus. Moreover, external memories can also be connected to a bus, which memories represent a data storage unit which as memories can correspond (that is, communicate) with processors or computers connected with the bus as well as with DMA (direct memory access) units which are likewise connected with the bus. A DMA unit contains a DMA device for direct memory access as well as a related device control. It is connected with a data terminal unit at which data are input or output or displayed.
All of these data processing units can correspond with one another by way of the bus, that is, exchange information which must always finally be transferred by a transmitting unit and stored by a receiving unit. For this memory addressing is required, for which purpose a transmitting unit generates an address signal and passes this on to the bus, which is transferred by the bus and goes to one or a plurality of other units, where after it is received it is verified whether the address information transmitted with it belongs to the address range of the respective memory which is present on the receiving unit. If this is not the case, then no further information is sent to the receiving unit. If the address information, however, is within the address range of the memory of a receiving unit, then the unit selected by the address signal is reached, and the memory of this unit can then receive further information to be transmitted from the transmitting unit by way of the bus.
Up to now the internal memories of processors which are connected with a multiple line system have been selectively addressed in such a way that one address word represents the address of the desired processor and another address word then represents the address of a storage location of the internal memory present in this processor. A disadvantage of such an addressing process consists in the time required for the two-step addressing. Besides this the two-step multiple line system must be specially built, since either successive time intervals requiring corresponding time control of the addressing, or, for parallel transmisson of the different address segments, individually assigned wire conductors are required. Another disadvantage consists on the special control complexity required for two different address segments in making connection with a desired memory.